The core content of this article is based on the speech delivered by Guo Zuorong, Senior Vice President of Research at TrendForce, at MTS2026, summarizing the key trends and challenges in the global wafer foundry market. In 2026, the revenue of the wafer foundry market is projected to grow by 19%, yet insufficient production capacity will continue to constrain supply chain development. TSMC will maintain its absolute dominance in the industry with a 72% share of global revenue, and the pricing and capacity expansion of its advanced processes are particularly critical.

Meanwhile, as of the end of 2025, robust demand for AI and automotive chips has driven the rapid advancement of advanced processes and packaging technologies. However, tight production capacity has also led to memory chip shortages and mounting cost pressures in the consumer electronics sector. Regionalized supply chains and the diversification of the AI chip ecosystem are emerging as key future trends. Despite substantial market growth, there are currently no clear signs of a market bubble.

2026 Wafer Foundry Market to Grow 19% but Fall Short of Demand

According to TrendForce forecasts, the global wafer foundry industry is expected to generate $203.2 billion in revenue in 2026, representing a 19% year-on-year growth, primarily driven by TSMC and AI applications. By region, in 2026, Chinese Taiwan will account for 78% of the combined revenue of the world’s top 10 wafer foundries, followed by mainland China at 8% and South Korea at 7%. By company, TSMC alone will contribute 72% of global revenue in 2026, with Samsung ranking second at 6.8% and SMIC third at 4.8%.

Looking at the projected 2026 revenue performance of major wafer foundries, TSMC’s revenue is expected to maintain a year-on-year growth rate of over 20%. In addition, Huahong Group, World Advanced Semiconductor, and Grace Semiconductor Manufacturing are forecast to achieve nearly 20% year-on-year growth. Samsung Electronics, GlobalFoundries, United Microelectronics Corporation (UMC), SMIC, and Tower Semiconductor are all expected to post around 5% year-on-year growth.

Guo Zuorong added that without TSMC, the global wafer foundry industry’s revenue growth would be limited to just 7.7% in 2026. Currently, the unit price of silicon wafers using TSMC’s 3nm/5nm/7nm processes ranges from $10,000 to over $20,000. TSMC’s advanced chip foundry service prices are projected to rise by 10% in 2026—the company plans to implement an annual price hike of approximately 5% over the next three years, with the unit price of 3nm wafers potentially exceeding $30,000.

As TSMC gradually ramps up mass production of more advanced process chips such as 1.6nm, 1.4nm, and 1nm, the unit price of related silicon wafers will climb further, and their revenue contribution will increase year by year. On this basis, the global advanced process segment is anticipated to grow by 29% in 2026—a figure that incorporates both price increases and growth from advanced packaging.

At present, demand for AI chips and automotive chips is the strongest. In fact, the growth rate of AI servers surged to 46% in 2024. Based on this benchmark, TrendForce initially predicted that "AI servers would maintain steady annual growth thereafter", but revised its 2026 growth forecast upward to 24% in the second half of 2025.

What has driven the rapid expansion in the AI server sector over the past six months? Guo Zuorong explained that it is primarily due to US-based cloud service providers (CSPs) accelerating the construction of AI infrastructure, investing heavily in building AI computing clusters (e.g., Amazon’s $125 billion and Microsoft’s $80 billion investments). This has triggered a chain reaction of full utilization of chip manufacturing capacity and shortages of flash memory and DRAM supplies.

According to his analysis, this round of memory shortages is also linked to the wafer foundry sector. "The more AI chips TSMC ships, the more severe the shortages of DRAM and flash memory will become." Against the backdrop of structural shortages, memory chip prices are expected to continue rising in 2026, placing greater pressure on the consumer electronics market. "End products have low profit margins, making it difficult for manufacturers to absorb costs internally. They may pass these costs on to consumers through price increases, which is projected to lead to a 2% year-on-year decline in smartphone and notebook shipments in 2026."

Demand for AI chips remains robust, particularly for high-performance computing chips such as HBM and DDR5, which is also driving demand for edge AI chips (e.g., NPUs). To pursue higher profits, wafer foundries are prioritizing the allocation of advanced process capacity to AI chip orders. However, limited adjustments to pricing strategies for mature processes mean that supply struggles to meet surging demand, exacerbating supply-demand imbalances in certain product categories.

CAGR and Capacity Utilization of 8/12-inch Wafers

In addition to analyzing supply-demand dynamics, Guo Zuorong also discussed the CAGR and capacity utilization of wafers. Between 2021 and 2030, the compound annual growth rate (CAGR) of 12-inch wafer capacity will reach 10.4%, with growth momentum primarily driven by the Chinese market. According to the financial reports of global semiconductor equipment manufacturers, the Chinese market typically contributes 30% to 40% of their revenue, with a CAGR of approximately 21.4%—significantly higher than the global average (6.2% for non-Chinese markets).

From 2021 to 2030, the growth of 8-inch wafer capacity will be relatively modest, maintaining a CAGR of around 1.2% through optimization and automation upgrades. Compared to 12-inch wafers, 8-inch wafers yield lower profit margins. In recent years, both wafer foundries and IDMs have intentionally reduced their 8-inch production lines to focus on 12-inch capacity, resulting in slow global growth of 8-inch wafer capacity. In the future, 8-inch wafers will follow the path of 6-inch wafers, with capacity continuing to contract in mature process segments and shifting toward high-value-added applications.

In recent years, TSMC has intensified its overseas deployment of advanced process capacity. By 2030, the share of advanced process capacity located in Chinese Taiwan is projected to drop to 55%, down from 66% in 2021. Meanwhile, the US share of advanced process capacity will rise significantly from 18% in 2021 to 28% in 2030, while the share of mainland China will decline slightly from 5% in 2021 to 4% in 2030.

In terms of mature process capacity distribution, two prominent shifts will occur: first, the share of Chinese Taiwan will plummet from 54% in 2021 to 26% in 2030; second, the share of mainland China will surge from 22% in 2021 to 52% in 2030.

This transformation is mainly driven by restrictions on mainland China’s expansion of advanced process capacity, prompting significant investments in mature process capacity over the past few years. As newly built 8-inch capacity comes online gradually, mainland China will account for over half of global mature process chip production by 2030. At the same time, foundries in Chinese Taiwan, led by TSMC, are shifting their focus to advanced processes and gradually reducing investment in mature processes, leading to a notable decline in their market share by 2030.

Turning to the capacity utilization rates of global wafer foundries, the utilization rate of 8-inch capacity is expected to decline in Q1 2026, followed by a recovery in Q2 and Q3, and a slight drop for some companies in Q4. Overall, the 8-inch capacity utilization rate in 2026 will remain flat compared to 2025. When broken down by foundry, the 8-inch capacity utilization rates can be divided into three tiers:

• Tier 1: Huahong Group, SMIC, and World Advanced Semiconductor, with utilization rates exceeding 90%. Huahong and SMIC primarily cater to domestic market demand. For foreign manufacturers seeking to gain in-depth access to the Chinese market, compliance with certain application requirements or policies may necessitate partnering with local foundries, thereby boosting the utilization rates of these enterprises. World Advanced Semiconductor maintains a utilization rate above 90% due to strong demand for AI-related PMIC orders.
• Tier 2: Powerchip Semiconductor Manufacturing Corporation (PSMC), TSMC, and GlobalFoundries, with utilization rates ranging from 70% to 90%. As TSMC’s core business does not focus on 8-inch wafers, its 8-inch capacity utilization rate hovers between 75% and 80%. GlobalFoundries’ 8-inch capacity utilization rate, previously between 70% and 75%, is projected to rise to 75% to 80% in 2026.
• Tier 3: Companies with utilization rates below 70%, represented by UMC and Samsung. Due to the high price sensitivity of the mature process market, UMC has opted to stabilize prices to protect profit margins, leading mature process customers to adopt a wait-and-see attitude and slow down wafer starts. Samsung, on the other hand, is intentionally reducing its 8-inch capacity allocation to redirect resources to other production lines. Additionally, the company’s failure to dispose of some outdated equipment has resulted in an 8-inch capacity utilization rate of only around 67%.

In 2026, the 12-inch capacity utilization rates of major wafer foundries will see an overall improvement. By Q4 2026, Grace Semiconductor Manufacturing, PSMC, and SMIC are expected to achieve 12-inch capacity utilization rates of 93%, 91%, and 90% respectively. GlobalFoundries, TSMC, Huahong Group, and UMC will post utilization rates of 87%, 86%, 84%, and 82% respectively, while Samsung Electronics’ 12-inch capacity utilization rate will remain at approximately 75%.

Guo Zuorong analyzed that Grace Semiconductor Manufacturing’s leading 12-inch capacity utilization rate is primarily driven by domestic circular economy demand, with its overall shipments set to increase steadily in 2026. In addition, PSMC and TSMC are also seeing a steady rise in capacity utilization rates. Samsung’s relatively low 12-inch capacity utilization rate stems from its weaker competitiveness in advanced processes. As of Q4 2025, Samsung’s 3nm yield rate was only around 30%, compared to TSMC’s over 80%. Samsung’s 2nm yield rate remains below 10%, while TSMC maintains a 2nm yield rate of around 80%.

Notably, TSMC’s capital expenditure scale far exceeds that of its peers. Its 2026 capital expenditure is projected to reach $47.708 billion, representing an 18% year-on-year increase. In contrast, while Samsung, SMIC, UMC, and other manufacturers will see slight increases in 2026 capital expenditure, their investment scales pale in comparison to TSMC. Overall, TSMC’s 2026 capital expenditure will exceed the combined total of the other nine major players, reflecting the company’s strong confidence in the market outlook.

Specifically, TSMC’s substantial investments will be allocated to advanced process R&D, advanced packaging capacity expansion, and the construction of global manufacturing bases. For example, in Chinese Taiwan, TSMC is advancing several key projects: the Hsinchu Baoshan fab has completed the deployment of 2nm technology and plans to introduce 1.4nm processes; the Taichung fab will also build a 1.4nm production line; and advanced packaging fabs under construction in Chiayi and other locations will require significant capital investment.

In addition, TSMC’s overseas expansion is progressing in parallel: the first fab in Arizona, USA, has been completed, and the second fab will adopt 2nm technology (only one generation behind TSMC’s fabs in Chinese Taiwan); the first fab in Kumamoto, Japan, is already in mass production, with the second fab currently in the planning stage; and the European Semiconductor Manufacturing Company (ESMC) fab in Germany, in which TSMC holds a 70% stake, is also advancing as scheduled.

Wafer Starts of the World’s Top 10 12-inch Wafer Foundries

Total wafer starts for both mature and advanced processes are projected to reach 3.326 million wafers in 2026, a 11% year-on-year increase from 3 million wafers in 2025. Of the newly added wafer starts, approximately 75% will be for mature processes and 25% for advanced processes.

Among advanced process nodes, the monthly production capacity of the 2nm process is expected to reach around 55,000 wafers, primarily contributed by TSMC. The 3nm capacity is concentrated in the hands of NVIDIA, AMD, and custom chips developed by major cloud vendors, with current monthly production capacity standing at only around 3,000 wafers.

For mature process nodes, monthly wafer starts for the 28nm/22nm node will reach 54,000 wafers, 45nm/40nm will hit 53,000 wafers, and 65nm/55nm and 90nm/80nm nodes will total 62,000 wafers. Approximately 77% of the newly added mature process capacity in 2026 will come from mainland China. As newly built capacity in mainland China gradually ramps up, the region’s share of global 28nm capacity will reach 36% in 2026, 40nm at 33%, 55nm at 28%, and 90nm at 3%.

By 2026, TSMC, Samsung, and Intel will advance to the N2P/A16, SF2P, and 14A nodes respectively. However, due to semiconductor equipment export restrictions, mainland China faces significant constraints on expanding advanced process capacity. Nevertheless, leveraging existing DUV lithography machines and multi-patterning technology, China is expected to evolve to an advanced process equivalent to TSMC’s 7nm, with further optimizations possible based on this equivalent 7nm process. This is the primary reason why mainland China has chosen an industrial development path that prioritizes accumulating experience in mature processes before gradually extending to advanced processes.

No Obvious Market Bubble in AI Demand

In the fields of advanced processes and advanced packaging, TSMC plans to mass-produce the S6 process node in 2026, which is essentially an enhanced version of the baseline 2nm technology. By 2028, TSMC will roll out next-generation processes such as A14, A12, and A10. Following the A12 node, TSMC will adopt GAA equipment, which is more advanced than EUV tools.

The 3nm process is currently the focal point of competition for AI chips. To alleviate capacity constraints at this node, TSMC has offered preferential terms to encourage Apple to shift part of its demand to the 2nm process, thereby freeing up more 3nm capacity for AI chips such as the AMD MI350 and NVIDIA Rubin. Currently, nearly all mainstream US AI chips are manufactured using the 3nm process.

TrendForce pointed out that global advanced packaging capacity surged by 82% year-on-year in 2025 and is expected to grow by a further 27% in 2026. Among this capacity, TSMC’s CoWoS technology accounts for the lion’s share. CoWoS is critical for integrating AI chips with HBM, and the profit margin of TSMC’s CoWoS business now exceeds that of its advanced processes, primarily due to lower production equipment costs. The unit price of a single advanced packaging wafer has risen from approximately $5,000 three years ago to $10,000, and is expected to climb further to $17,000 in the future. TSMC has clearly outlined plans to establish a pilot line for its CoPoS technology in 2026, with mass production targeted for late 2028 to 2029. CoWoP, a derivative technology of CoWoS, is expected to progress in tandem.

In Guo Zuorong’s view, the key future trends in the semiconductor industry will be reflected in two main aspects:

1. Significant Regionalization of the Supply ChainThe Chinese market is actively promoting a domestic economic cycle. When international IDM manufacturers (such as Infineon, NXP, Texas Instruments, and ON Semiconductor) produce in China, they tend to select local foundries such as TSMC’s Nanjing fab or SMIC. To supply markets outside China, however, they primarily rely on TSMC or UMC for manufacturing. This strategy of choosing different foundry partners based on regional markets is essentially a common practice adopted by countries worldwide to strengthen the security of their domestic industrial chains.
2. Diversification of the AI Chip Ecosystem from CentralizationWhile NVIDIA maintains dominance with its high-margin products, the high costs have prompted cloud service giants such as Google, Microsoft, and AWS to develop custom ASIC chips. These companies typically entrust IP design to firms like Broadcom and MediaTek, before outsourcing manufacturing to TSMC, Samsung, or Intel. This has created an emerging software-hardware co-optimization ecosystem. Nevertheless, both NVIDIA GPUs and various ASICs require integration with high-end memory such as HBM or DDR5, which perpetuates tight memory capacity and exacerbates overall chip supply shortages.

Overall, amid the current AI boom, TSMC is continuously expanding capacity and dynamically adjusting production plans. Feedback from TSMC itself and its downstream server contract manufacturers (such as Wiwynn, Hon Hai Precision Industry, and Quanta Computer) indicates that demand for AI servers will continue to grow through 2026, with no obvious signs of a market bubble emerging as yet.